View MAX1997ETJ_1272684.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2638; Rev 0; 10/02
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
General Description
The MAX1997/MAX1998 provide the voltages required for active-matrix, thin-film transistor liquid-crystal displays (TFT LCDs). Both combine a high-performance step-up regulator with two linear-regulator controllers, input protection switch control, and flexible sequence programming. The MAX1997 contains two additional linearregulator controllers and a VCOM buffer. The MAX1997/ MAX1998 can operate from input supplies of 2.7V to 5.5V and feature multiple levels of protection circuitry, making them complete power-supply systems for displays. The main DC-DC converter provides the regulated supply voltage for the display's source-driver ICs. The converter is a high-frequency (up to 1.5MHz) step-up regulator with an integrated 14V N-channel MOSFET that allows the use of ultra-small inductors and ceramic capacitors while achieving efficiencies over 85%. Its current-mode control architecture provides fast transient response to pulsed loads. Internal soft-start and cycle-by-cycle current limit help prevent input surge currents. The positive and negative linear-regulator controllers postregulate charge-pump outputs for TFT gate-on and gate-off supplies. Both linear-regulator controllers, as well as the step-up regulator, have supply-sequencing control inputs. The three outputs can be sequenced in any order by selecting the appropriate external components. The MAX1997 features a high-current backplane driver (VCOM). This buffer provides peak currents exceeding 300mA (typ) and requires only a 0.47F output filter capacitor. The MAX1997's two additional linear-regulator controllers can be used to build the gamma reference voltage and a logic supply. The MAX1997/MAX1998 have a unique input switch control that can replace the typical input supply fuse. When a fault is detected, the regulator is disconnected from the input supply. The fault detector monitors all the regulated output voltages and the current from the input supply. In addition, the MAX1997/MAX1998 enter shutdown when the internal over-temperature threshold is reached. The MAX1997 is available in a 32-pin thin QFN package and the MAX1998 is available in a 20-pin thin QFN package. Both packages have a maximum thickness of 0.8mm suitable for ultra-thin LCD panels. o 2.7V to 5.5V Input Supply Range o Adjustable (Up to +13V) Output Voltage for Source-Driver ICs o Integrated High-Efficiency Power MOSFET o Linear-Regulator Controllers for TFT Gate-On and Gate-Off Supplies o High-Current VCOM Buffer (MAX1997 Only) o Two Additional Linear-Regulator Controllers (MAX1997 Only) o Programmable Power-Up Sequencing o Multiple Overload Protection with Thermal Shutdown o 1A Shutdown Current o 32-Pin/20-Pin Thin QFN Packages
Features
MAX1997/MAX1998
Ordering Information
PART MAX1997ETJ MAX1998ETP TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 32 Thin QFN 5mm x 5mm 20 Thin QFN 5mm x 5mm
Pin Configurations
FREQ
GATE OCP
20
19
IN
18
17
PGND CT ONN ONP ON2
1 2 3 4 5 10 6 7 8 9
16 15 14
OCN
TOP VIEW
TGNDA LX DRVP FBP FB
MAX1998
13 12 11
DRVN
FBN
DRVA
REF
Notebook Computer Displays LCD Monitors Car Navigation Displays
THIN QFN 5mm x 5mm
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
GND
Applications
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
ABSOLUTE MAXIMUM RATINGS
IN, SHDN, FB, FBP, FBN, FB1, FB2, ONDC, ONP, ONN, ON2, TGNDA, TGNDB to GND.............-0.3V to +6V PGND to GND .....................................................................0.3V LX, VDDB to GND....................................................-0.3V to +14V DRVP, DRV1, DRV2, DRVA to GND .......................-0.3V to +30V REF, FREQ, GATE, OCN, OCP, CT, PFLT to GND ..................................................-0.3V to VIN + 0.3V DRVN to GND ..........................................VIN - 28V to VIN + 0.3V FBPB, FBNB, OUTB to GND.......................-0.3V to VDDB + 0.3V OUTB Continuous Output Current ..................................100mA MAX1997 Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (derate 21.2mW/C above +70C) ............................1702mW MAX1998 Continuous Power Dissipation (TA = +70C) 20-Pin Thin QFN (derate 20mW/C above +70C) ...............................1600mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 3V, VDDB = 10V, SHDN = ONDC = FREQ = IN, CREF = 0.22F, PGND = GND, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER IN Supply Range IN Undervoltage Lockout Threshold 350mV (typ) hysteresis VIN rising VIN falling CONDITIONS MIN 2.7 2.5 2.2 2.7 2.35 0.54 0.476 0.1 1.231 1.225 1.250 1.250 160 VOCN = VOCP = 1.5V to 0.8V x VIN VOCN = VOCP = 0.8V x VIN -5 -50 1.5 +5 +50 0.8 x VIN 21.8 43.6 87.2 5 10 15 200 200 VIN FREQ = IN Operating Frequency FREQ unconnected FREQ = GND 0.637 1.5 0.75 0.375 0.863 MHz 13 A V ms TYP MAX 5.5 2.9 2.5 1.25 1 1 1.269 1.275 A V C mV nA V UNITS V V
IN Quiescent Current (Note 1) IN Shutdown Current REF Output Voltage Thermal Shutdown OVERCURRENT COMPARATOR Input Offset Voltage Input Bias Current OCN, OCP Input Common-Mode Range FAULT TIMER
VFB = VFBP = VFB1 = VFB2 = 1.5V, VFBN = 0 (MAX1997 only) VFB = VFBP = 1.5V, VFBN = 0 (MAX1998 only) V SHDN = 0, VIN = 5.5V -2A < IREF < 50A -2A < IREF < 75A
mA
PFLT = GND (MAX1997 only) Fault Timer Period GATE Output Sink Current During Slew GATE Output Pulldown Resistance GATE Output Pullup Resistance MAIN STEP-UP REGULATOR Output Voltage Range PFLT unconnected (MAX1997 only) PFLT = IN, or MAX1998 VGATE = 1.5V during turn-on transition VGATE < 0.5V
2
_______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 3V, VDDB = 10V, SHDN = ONDC = FREQ = IN, CREF = 0.22F, PGND = GND, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER Oscillator Maximum Duty Cycle FB Regulation Voltage FB Fault Trip Level FB Load Regulation FB Line Regulation FB Input Bias Current LX On-Resistance LX Leakage Current LX Current Limit LX RMS Current Rating Soft-Start Period Soft-Start Step Size POSITIVE LINEAR-REGULATOR CONTROLLERS (REG P, REG 1, AND REG 2) IDRVP = 100A FB_ Regulation Voltage FB_ Fault Trip Level FB_ Input Bias Current IDRV1 = 1350A (MAX1997 only) IDRV2 = 335A (MAX1997 only) VFB_ falling VFB_ = 1.25V VDRVP = 10V, IDRVP = 0.05mA to 1mA FB_ Effective Load Regulation Error (Transconductance) VDRV1 = 10V, IDRV1 = 0.5mA to 5mA (MAX1997 only) VDRV2 = 10V, IDRV2 = 0.1mA to 2mA (MAX1997 only) IDRVP = 100A, 2.7V < VIN < 5.5V FB_ Line (IN) Regulation Error IDRV1 = 1350A, 2.7V < VIN < 5.5V (MAX1997 only) IDRV2 = 335A, 2.7V < VIN < 5.5V (MAX1997 only) Bandwidth DRVP Sink Current DRV1 Sink Current (MAX1997 only) DRV2 Sink Current (MAX1997 only) DRV_ Leakage Current Soft-Start Period Soft-Start Step Size NEGATIVE LINEAR-REGULATOR CONTROLLER (REG N) FBN Regulation Voltage FBN Fault Trip Level FBN Input Bias Current IDRVN = 100A VFBN rising VFBN = 0V 95 325 -200 125 370 155 475 +200 mV mV nA VFB_ = 1.5V, VDRV_ = 28V VFB_ = 1.1V, VDRV_ = 10V (Note 2) 1000 2 5 5 3.3 18 15 0.1 4096/fOSC VREF/32 10 A s V mA kHz 1 mV -1.5 -2 % 0.96 -250 1.00 1.04 +250 V nA 1.225 1.250 1.275 V (Note 2) 4096/fOSC VREF/32 VLX = 13V 1.6 ILX = 200mA VFB falling IMAIN = 0 to full load VIN = 2.7V to 5.5V VFB = 1.5V -100 250 0.01 2.1 CONDITIONS MIN 80 1.229 0.96 TYP 85 1.242 1.00 -1.6 0.2 0.4 +100 450 20 2.8 1.4 MAX 90 1.254 1.04 UNITS % V V % %/V nA m A A A s V
MAX1997/MAX1998
_______________________________________________________________________________________
3
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 3V, VDDB = 10V, SHDN = ONDC = FREQ = IN, CREF = 0.22F, PGND = GND, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER FBN Effective Load Regulation Error (Transconductance) FBN Line (IN) Regulation Error Bandwidth DRVN Source Current DRVN Leakage Current Soft-Start Period Soft-Start Step Size VCOM BUFFER (MAX1997 only) VDDB Supply Range VDDB Supply Current VDDB Shutdown Current Input Offset Voltage Input Bias Current Input Offset Current Input Common-Mode Range Power-Supply Rejection Ratio Common-Mode Rejection Ratio Gain-Bandwidth Product Load-Transient Settling Time Transconductance Output Current Drive LOGIC SIGNALS (SHDN, ONDC) Input Low Voltage Input High Voltage Input Current CONTROL INPUTS AND OUTPUTS ONN, ONP, ON2 Comparator Offset DRVA Sink Current DRVA Off-Leakage CT Source Current CT Discharge Resistance FREQ, PFLT Input Low Voltage FREQ, PFLT Input Middle Voltage FREQ, PFLT Input High Voltage FREQ, PFLT Input Current FREQ, PFLT = GND or IN VIN - 1 -50 +50 VIN/2 V A V ON _ - VCT, VCT = 1.25V 50mV VDRVA = 10V, VCT = 1.25V, V ON2 = 2V VDRVA = 28V, VCT = 1.25V, V ON2 = 1V VCT = 1V VCT = 1V 2.5 -50 5 11 0.1 5 15 10 7.5 100 1 +50 mV mA A A V 100mV typ hysteresis 1.6 0.01 1 0.4 V V A VFBPB = VFBNB = 5V, VDDB = 9V VDDB = 13V, SHDN = ONDC = GND VFBPB = 2.5V, no load VFBPB = VFBNB = 1.2V to VDDB - 1.2V VFBPB = VFBNB = 1.2V to VDDB - 1.2V VDDB = 4.5V to 13V VDDB = 4.5V to 13V, VFBPB = 2.25V VFBPB = VFBNB = 1.2V to VDDB - 1.2V Small signal RL = 25, CL = 10nF, VDRIVE = 9V, settle to within 10mV (Note 4) Small signal (1mV overdrive) Large signal (30mV overdrive) 100mV overdrive, VOUTB = 3V or 7V 150 -100 1.2 70 70 1/6CL 5 0.3 7.2 300 -5 4.5 367 3.5 13 900 13 +5 1 +100 VDDB 1.2 V A A mV A nA V dB dB Hz s S mA CONDITIONS VDRVN = -10V, IDRVN = 50A to 1mA IDRVN = 100A, 2.7V < VIN < 5.5V (Note 2) VFBN = 200mV, VDRVN = -10V VFBN = -0.1V, VDRVN = -20V 1000 2 4.2 0.1 4096/fOSC VREF/32 10 MIN TYP 18 1 MAX 25 UNITS mV mV kHz mA A s V
4
_______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
ELECTRICAL CHARACTERISTICS
(VIN = 3V, VDDB = 10V, SHDN = ONDC = FREQ = IN, CREF = 0.22F, PGND = GND, TA = -40C to +85C, unless otherwise noted.) (Note 3)
PARAMETER IN Supply Range IN Undervoltage Lockout Threshold 350mV typ hysteresis VIN rising VIN falling CONDITIONS MIN 2.7 2.5 2.2 TYP MAX 5.5 2.9 2.5 1.25 1 1.223 1.218 -5 -50 1.5 1.270 1.280 +5 +50 0.8 x VIN 13 2 0.937 0.50 92 1.260 1.04 +100 450 1.6 IDRVP = 100A FB_ Regulation Voltage FB_ Fault Trip Level IDRV1 = 1350A (MAX1997 only) IDRV2 = 335A (MAX1997 only) VFB_ falling VDRVP = 10V, IDRVP = 0.05mA to 1mA FB_ Effective Load Regulation Error (Transconductance) VDRV1 = 10V, IDRV1 = 0.5mA to 5mA (MAX1997 only) VDRV2 = 10V, IDRV2 = 0.1mA to 2mA (MAX1997 only) DRVP Sink Current DRV1 Sink Current (MAX1997 Only) DRV2 Sink Current (MAX1997 Only) VFB_ = 1.1V, VDRV_ = 10V 1 5 5 mA -2.5 % 0.96 1.04 V 1.213 1.288 V 2.8 % V V nA m A MHz V UNITS V V
MAX1997/MAX1998
IN Quiescent Current (Note 1)
VFB = VFBP = VFB1 = VFB2 = 1.5V, VFBN = 0 (MAX1997 only) VFB = VFBP = 1.5V, VFBN = 0 (MAX1998 only) -2A < IREF < 50A -2A < IREF < 75A VOCN = VOCP = 1.5V to 0.8V x VIN VOCN = VOCP = 0.8V x VIN
mA
REF Output Voltage OVERCURRENT COMPARATOR Input Offset Voltage Input Bias Current OCN, OCP Input Common-Mode Range MAIN STEP-UP REGULATOR Output Voltage Range
mV nA V
VIN FREQ = IN 1 0.563 0.25 78 ILX = 200mA VFB falling VFB = 1.5V 1.215 0.96 -100 FREQ unconnected FREQ = GND
V
Operating Frequency Oscillator Maximum Duty Cycle FB Regulation Voltage FB Fault Trip Level FB Input Bias Current LX On-Resistance LX Current Limit
POSITIVE LINEAR-REGULATOR CONTROLLERS (REG P, REG 1, AND REG 2)
_______________________________________________________________________________________
5
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, VDDB = 10V, SHDN = ONDC = FREQ = IN, CREF = 0.22F, PGND = GND, TA = -40C to +85C, unless otherwise noted.) (Note 3)
PARAMETER NEGATIVE LINEAR-REGULATOR CONTROLLER (REG N) FBN Regulation Voltage FBN Fault Trip Level FBN Effective Load Regulation Error (Transconductance) DRVN Source Current VCOM BUFFER (MAX1997 only) VDDB Supply Range VDDB Supply Current Input Offset Voltage Input Bias Current Input Common-Mode Range Out Current Drive LOGIC SIGNALS (SHDN, ONDC) Input Low Voltage Input High Voltage CONTROL INPUTS AND OUTPUTS FREQ, PFLT Input Low Voltage FREQ, PFLT Input High Voltage FREQ, PFLT Input Current FREQ, PFLT = GND or IN VIN - 1 -50 +50 1 V V A 100mV typ hysteresis 1.6 0.4 V V VFBPB = VFBNB = 5V, VDDB = 9V VFBPB = 2.5V, no load VFBPB = VFBNB = 1.2V to VDDB - 1.2V VDDB = 4.5V to 13V 100mV overdrive, VOUTB = 3V or 7V 1.2 150 -5 4.5 13 900 +5 1 VDDB 1.2 V A mV A V mA IDRVN = 100A VFBN rising VDRVN = -10V, IDRVN = 0.05mA to 5mA VFBN = 200mV, VDRVN = -10V 1 95 325 155 475 30 mV mV mV mA CONDITIONS MIN TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4:
Quiescent current does not include switching losses. Guaranteed by design, not production tested. Specifications to -40C are guaranteed by design, not production tested. The VCOM buffer load transient settling time is measured with the following circuit:
VSOURCE 9V 20k VGAMMA 8.6V 20k FBNB GND 1F MAX1997 OUTB RL 25 Vx CL 10nF VDRIVE 8V VDDB 1F
FBPB
6
_______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 3.3V, V MAIN = 9V, V G_ON = 20V, VG_OFF = -7V, V LOGIC = 2.5V, V GAMMA = 8.6V, T A = +25C, unless otherwise noted.)
STEP-UP REGULATOR EFFICIENCY vs. LOAD CURRENT (VMAIN = 9V)
MAX1997 toc01
STEP-UP REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (VMAIN = 9V)
MAX1997 toc02
STEP-UP REGULATOR EFFICIENCY vs. LOAD CURRENT (VMAIN = 13V)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 VIN = 2.7V
MAX1997 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 10 100 VIN = 2.7V VIN = 3.3V VIN = 5.5V
9.1 9.0 OUTPUT VOLTAGE (V) 8.9 VIN = 2.7V 8.8 8.7 8.6 8.5 VIN = 3.3V VIN = 5.5V
100 VIN = 5.5V VIN = 3.3V
0 1 10 100 1000 1 10 100 1000 LOAD CURRENT (mA) LOAD CURRENT (mA)
1000
LOAD CURRENT (mA)
STEP-UP REGULATOR EFFICIENCY vs. LOAD CURRENT
MAX1997 toc04
STEP-UP REGULATOR SWITCHING FREQUENCY vs. INPUT VOLTAGE
VMAIN = 9V IMAIN = 200mA FREQUENCY = VIN
MAX1997 toc05
STEP-UP REGULATOR NORMAL OPERATION (200mA LOAD)
MAX1997 toc06
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 750kHz OPERATION L = 4.7H COILCRAFT LPO25061B-472 COUT = 3 x 4.7F/10V X7R CERAMIC 10 100 VIN = 5.5V VIN = 3.3V VIN = 2.7V
1700 1500 FREQUENCY (kHz) 1300 1100
10V A 5V 0 9.02V
900 700 500 300
FREQUENCY = OPEN
B
9V 8.98V
FREQUENCY = 0 C
1A 0
1000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1s/div A: VLX, 5V/div B: VMAIN = 9V, 20mV/div, AC-COUPLED C: INDUCTOR CURRENT, 1A/div
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
STEP-UP REGULATOR LOAD TRANSIENT RESPONSE (WITHOUT LAG COMPENSATION, FIGURE 1)
MAX1997 toc07
A
200mA 0 9V
B
8.95V
1A C 0.5A 0 10s/div A: IMAIN = 0 TO 200mA, 200mA/div B: VMAIN = 9V, 50mV/div, AC-COUPLED C: INDUCTOR CURRENT, 500mA/div
_______________________________________________________________________________________
7
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 3.3V, V MAIN = 9V, V G_ON = 20V, VG_OFF = -7V, V LOGIC = 2.5V, V GAMMA = 8.6V, T A = +25C, unless otherwise noted.)
STEP-UP REGULATOR LOAD TRANSIENT RESPONSE (WITH LAG COMPENSATION, FIGURE 9)
MAX1997 toc08
STEP-UP REGULATOR LOAD TRANSIENT RESPONSE (2s PULSES) (WITHOUT LAG COMPENSATION, FIGURE 1)
MAX1997 toc09
STEP-UP REGULATOR LOAD TRANSIENT RESPONSE (2s PULSES) (WITH LAG COMPENSATION, FIGURE 9)
MAX1997 toc10
A
200mA 0 9V
A
1A 50mA
A
1A 50mA
B
8.9V
B
9V 8.9V
B
9V 8.9V 2A
1A C 0.5A 0 10s/div A: IMAIN = 0 TO 200mA, 200mA/div B: VMAIN = 9V, 50mV/div, AC-COUPLED C: INDUCTOR CURRENT, 500mA/div R7 = 76.8k, R8 = 12.1k, R10 = 1.5k, C10 = 470pF C
2A 1A 0 4s/div A: IMAIN = 50mA TO 1A, 1A/div B: VMAIN = 9V, 100mV/div, AC-COUPLED C: INDUCTOR CURRENT, 1A/div C
1A 0 10s/div A: IMAIN = 50mA TO 1A, 1A/div B: VMAIN = 9V, 100mV/div, AC-COUPLED C: INDUCTOR CURRENT, 1A/div R7 = 76.8k, R8 = 12.1k, R10 = 1.5k, C10 = 470pF
STEP-UP REGULATOR SOFT-START
MAX1997 toc11
POWER-UP SEQUENCE
5V 0 5V A 0 10V B 0 20V C 10V 0 0 D 0 -10V 4ms/div A: VMAIN, 10V/div B: VSOURCE, 10V/div C: VGATE_ON, 10V/div D: VGATE_OFF, 10V/div VONN < VONP < VON2 D C B
MAX1997 toc12
POWER-UP SEQUENCE
10V A 0 10V 0 20V 10V 0 0 -10V 4ms/div A: VMAIN, 10V/div B: VSOURCE, 10V/div C: VGATE_ON, 10V/div D: VGATE_OFF, 10V/div VONN > VONP > VON2
MAX1997 toc13
10V
A
B
0 5V
C
0 10V
D
5V 1ms/div A: VSHDN, 5V/div B: VGATE, 5V/div C: VDRAIN, 5V/div D: VMAIN, 5V/div
8
_______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 3.3V, V MAIN = 9V, V G_ON = 20V, VG_OFF = -7V, V LOGIC = 2.5V, V GAMMA = 8.6V, TA = +25C, unless otherwise noted.)
REG P (GATE-ON VOLTAGE) LOAD REGULATION
MAX1997 toc14
REG N (GATE-OFF VOLTAGE) LOAD REGULATION
MAX1997 toc15
REG 1 (LOGIC SUPPLY) LOAD REGULATION
MAX1997 toc16
0 OUTPUT-VOLTAGE VARIATION (%)
0 OUTPUT-VOLTAGE VARIATION (%)
0 OUTPUT-VOLTAGE VARIATION (%)
-0.05
-0.08
-0.2
-0.10
-0.16
-0.4
-0.15
-0.24
-0.6
-0.20
-0.32
-0.8
-0.25 0.1 1 LOAD CURRENT (mA) 10
-0.40 0.1 1 LOAD CURRENT (mA) 10
-1.0 1 10 100 1000 LOAD CURRENT (mA)
REG 2 (GAMMA REFERENCE) LOAD REGULATION
MAX1997 toc17
REG 1 (LOGIC SUPPLY) LOAD TRANSIENT RESPONSE
MAX1997 toc18
REG 2 (GAMMA REFERENCE) VMAIN TRANSIENT REJECTION
300mA 200mA A
0 OUTPUT-VOLTAGE VARIATION (%)
MAX1997 toc19
20V 0 8.62V
-0.04
A -0.08 100mA 0 -0.12
B
8.60V 8.58V
C -0.16 2.5V B 2.49V D 4s/div A: VLX, 20V/div B: VGAMMA = 8.6V, 20mV/div, AC-COUPLED C: VMAIN = 9V, 200mV/div, AC-COUPLED D: IMAIN = 0 TO 1A, 1A/div
9.0V 8.8V 1A 0
-0.20 0.1 1 LOAD CURRENT (mA) 10 40s/div A: LOAD CURRENT, 0 TO 250mA, 100mA/div B: VLOGIC = 2.5V, 10mV/div, AC-COUPLED
_______________________________________________________________________________________
9
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 3.3V, V MAIN = 9V, V G_ON = 20V, VG_OFF = -7V, V LOGIC = 2.5V, V GAMMA = 8.6V, T A = +25C, unless otherwise noted.)
OVERCURRENT PROTECTION RESPONSE TO OVERLOAD DURING STARTUP
MAX1997 toc20
OVERCURRENT PROTECTION RESPONSE TO OVERLOAD DURING NORMAL OPERATION
10V 5V 0 5V A
MAX1997 toc21
REFERENCE VOLTAGE vs. LOAD CURRENT
MAX1997 toc22
10V 5V REFERENCE VOLTAGE (V) 0 5V
1.250
A
1.249
B 0 20V C D -10V 20ms/div A: VMAIN, 5V/div B: VGATE, 5V/div C: VG_ON, 10V/div D: VG_OFF, 10V/div 10V 0
B 0 20V C D -10V 20ms/div A: VMAIN, 5V/div B: VGATE, 5V/div C: VG_ON, 10V/div D: VG_OFF, 10V/div 10V 0
1.248
1.247
1.246 1 10 LOAD CURRENT (A) 100
LX CURRENT LIMIT vs. INPUT VOLTAGE
MAX1997 toc23
VCOM BUFFER TRANSCONDUCTANCE vs. TEMPERATURE
LARGE-SIGNAL TRANSCONDUCTANCE
MAX1997 toc24
VCOM LOAD TRANSIENT RESPONSE (CIRCUIT OF PAGE 6, NOTE 4)
MAX1997 toc25
2.2 TA = -40C 2.1 CURRENT LIMIT (A)
10
1A 0 -1A
A
TRANSCONDUCTANCE (S)
8
2.0
TA = +25C
6 B 4
3.8V 3.6V 3.4V 20V SMALL-SIGNAL TRANSCONDUCTANCE -40 -20 0 20 40 60 80 100 C 0 -20V TEMPERATURE (C) 4s/div A: LOAD CURRENT, 1A/div B: VOUTB = 3.6V, 200mV/div, AC-COUPLED C: VX, 20V/div
1.9
1.8 TA = +85C 1.7 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V)
2
0
Pin Description
PIN MAX1997 1 2 MAX1998 -- 1 NAME TGNDB PGND FUNCTION Internal Connection. Connect this pin to ground. Do not leave this pin floating. Power Ground. PGND is the source of the N-channel power MOSFET. Connect PGND to the star ground at the device's backside pad. Logic Linear-Regulator (REG 1) Base Drive. Open drain of an internal N-channel MOSFET. Connect DRV1 to the base of an external PNP linear regulator pass transistor. (See the Pass Transistor Selection section).
3
--
DRV1
10
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
Pin Description (continued)
PIN MAX1997 4 MAX1998 -- NAME FUNCTION Logic Linear-Regulator (REG 1) Feedback Input. FB1 regulates at 1.25V nominal. Connect FB1 to the center tap of a resistive voltage-divider between the REG 1 output and the analog ground (GND) to set the output voltage. Place the resistive voltage-divider close to the pin. Sequence Timing Control Input. Connect a capacitor from this pin to GND. This timing capacitor controls the turn-on of REG P, REG N, REG 2, and DRVA. The sequence timing block is enabled, together with the main step-up regulator, when ONDC goes high. Then an internal 5A current source charges the timing capacitor from 0V to VIN, which sets the turnon delay. A discharge switch keeps CT at GND when the sequence timing block is disabled. (See the Power-Up Sequencing and Inrush Current Control section.) Gate-Off Linear-Regulator (REG N) Sequence Control Input. REG N is enabled when SHDN is high, the gate to the input P-channel MOSFET is low, ONDC is high, and VCT > V ON N. (See the Power-Up Sequencing and Inrush Current Control section.) Gate-On Linear-Regulator (REG P) Sequence Control Input. REG P is enabled when SHDN is high, the gate to the input P-channel MOSFET is low, ONDC is high, and VCT > V ONP. (See the Power-Up Sequencing and Inrush Current Control section.) Gamma Linear-Regulator (REG 2) Sequence Control Input. REG 2 is enabled when SHDN is high, the gate to the input P-channel MOSFET is low, ONDC is high, and VCT > V ON 2. ON2 also controls the DRVA open-drain output, which is typically used to turn on an N-channel MOSFET between the step-up regulator output and the source driver ICs' supply pins. (See the Power-Up Sequencing and Inrush Current Control section.) Gate-Off Linear-Regulator (REG N) Base Drive. Open drain of an internal P-channel MOSFET. Connect DRVN to the base of an external NPN linear regulator pass transistor. (See the Pass Transistor Selection section.) Gate-Off Linear-Regulator (REG N) Feedback Input. FBN regulates to 125mV nominal. Connect FBN to the center tap of a resistive voltage-divider between the REG N output and the reference voltage (REF) to set the output voltage. Place the resistive voltage-divider close to the pin. Open-Drain Sequence Output. The DRVA open-drain output is controlled by ON2. DRVA is typically used to turn on an N-channel MOSFET between the step-up regulator output and the source-driver ICs' supply pins. DRVA is high impedance when SHDN is high, the gate to the input P-channel MOSFET is low, ONDC is high, and VCT > V ON2. Otherwise, DRVA connects to ground. (See the Power-Up Sequencing and Inrush Current Control section.) Internal Reference Bypass Terminal. Connect a 0.22F ceramic capacitor from REF to the analog ground (GND). External load capability is at least 75A. Analog Ground. VCOM Buffer Inverting Input. (See the VCOM Buffer section.) VCOM Buffer Output. Requires a minimum 0.47F ceramic filter capacitor to GND. Place the capacitor as close as possible to OUTB. VCOM Buffer Supply Input. Bypass to GND with a 0.47F capacitor as close as possible to the pin. VCOM Buffer Noninverting Input. (See the VCOM Buffer section.) Gamma Linear-Regulator (REG 2) Feedback Input. FBP regulates to 1.25V nominal. Connect FB2 to the center tap of a resistive voltage-divider between the REG 2 output and the analog ground (GND) to set the output voltage. Place the divider close to the pin.
MAX1997/MAX1998
FB1
5
2
CT
6
3
ONN
7
4
ONP
8
5
ON2
9
6
DRVN
10
7
FBN
11
8
DRVA
12 13 14 15 16 17 18
9 10 -- -- -- -- --
REF GND FBNB OUTB VDDB FBPB FB2
______________________________________________________________________________________
11
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Pin Description (continued)
PIN MAX1997 19 MAX1998 -- NAME FUNCTION Gamma Linear-Regulator (REG 2) Base Drive. Open drain of an internal N-channel MOSFET. Connect DRV2 to the base of an external PNP linear regulator pass transistor. (See the Pass Transistor Selection section.) Main Step-Up Regulator Feedback Input. Connect FB to the center tap of a resistive voltagedivider between the main output (VMAIN) and the analog ground (GND) to set the main stepup regulator output voltage. (See the Main Step-Up Regulator, Output Voltage Selection section.) Place the resistive voltage-divider close to the pin. Gate-On Linear-Regulator (REG P) Feedback Input. FBP regulates to 1.25V nominal. Connect FBP to the center tap of a resistive voltage-divider between the REG P output and the analog ground (GND) to set the output voltage. Place the resistive voltage-divider close to the pin. Gate-On Linear-Regulator (REG P) Base Drive. Open drain of an internal N-channel MOSFET. Connect DRVP to the base of an external PNP linear-regulator pass transistor. (See the Pass Transistor Selection section.) Switching Node. Drain of the internal N-channel power MOSFET for the main step-up regulator. Internal Connection. Connect this pin to ground. Do not leave this pin floating. Overcurrent Comparator Inverting Input. Connect OCN to the center tap of a resistive voltage-divider connected to the drain of the external input protection P-channel MOSFET. (See the Input Overcurrent Protection section.) If unused, connect OCN to REF. Overcurrent Comparator Noninverting Input. Connect OCP to the center tap of a resistive voltage-divider connected to the source of the external input protection P-channel MOSFET. The voltage on OCP sets the input overcurrent threshold. (See the Input Overcurrent Protection section.) If unused, connect OCP to GND. Gate-Drive Output to the External Input Protection P-Channel MOSFET. (See the Input Overcurrent Protection section.) If unused, leave GATE unconnected. Fault Timer Select Input. Pull PFLT above its logic high threshold (0.7 x VIN) to set the fault delay period to 87ms. Pull PFLT below its logic low threshold (0.3 x VIN) to set the fault delay period to 22ms. Leave PFLT unconnected to set the fault delay period to 44ms. The fault delay period for the MAX1998 is fixed at 87ms. Supply Input. The supply voltage powers all the control circuitry. The input voltage range is from 2.7V to 5.5V. Bypass IN to GND with a 0.47F ceramic capacitor. Place the capacitor within 5mm of IN. Step-Up Regulator Logic Control Input. The step-up regulator, VCOM buffer, and the sequence timing block are enabled when ONDC is high and disabled when ONDC is low. Frequency Select Input. Pull FREQ above its logic high threshold (0.7 x VIN) to set the main step-up regulator switching frequency to 1.5MHz. Pull FREQ below its logic low threshold (0.3 x VIN) to set the frequency to 375kHz. Leave FREQ unconnected to set the frequency to 750kHz. Active-Low Shutdown Control Input. All the sections of the device are disabled and the GATE pin goes high when SHDN is below its 0.4V logic low threshold. Pull SHDN above its 1.6V logic high threshold to enable the device. Do not leave SHDN unconnected.
DRV2
20
11
FB
21
12
FBP
22
13
DRVP
23 24 25
14 15 16
LX TGNDA OCN
26
17
OCP
27
18
GATE
28
--
PFLT
29
19
IN
30
--
ONDC
31
20
FREQ
32
--
SHDN
12
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
VIN 2.7V TO 5.5V P1 C2 10F 6.3V R4 43.2k L1 3.0H LX D1 C4 4.7F 10V VMAIN 9V C5 4.7F 10V C6 4.7F 10V
R5 150k R9 1M D5
R1 10 R3 150k
R2 51.1k
C7 1000pF R24 150k
C8 100pF 27 26 29 GATE OCP IN
25 OCN
23 LX
R7 7.68k
C9 0.01F FB 20 VSOURCE 9V N1 C11 0.47F DRVA 11 R10 2.2k R6 100k
C1 0.47F
28 32 30 31
PFLT SHDN ONDC FREQ R8 1.21k
R77 510 C12 1F Q1 VLOGIC 2.5V C13 10F LX 5 C16 0.1F REF D6 C17 0.22F 12 CT R88 12.4k
3
DRV1 DRV2
19
Q2
4 FB1 R99 12.4k C28 1000pF FB2 18 R12 20k REF GND VDDB FBPB FBNB OUTB 16 17 14 15 C15 1F VVCOM R11 118k C14 2.2F
VGAMMA 8.6V
MAX1997
R13 20k
C18 0.1F D2 C19 0.1F
13
R15 6.8k
R14 20k
Q4 R16 150k C20 0.47F
9
DRVN LX D3 C22 0.1F C23 0.1F
VG_OFF -7V
10
FBN
R18 6.8k
D4
REF
R17 24.3k
C24 0.1F DRVP 22 R19 301k Q3 VG_ON 20V
C25 0.1F
8 R21 39k 7 R22 39k 6 R23 39k
FBP ON2
21 R20 20k
C26 1F C27 1000pF
ONP
ONN
TGNDA TGNDB PGND 2
24 1
ANALOG GROUND (GND)
POWER GROUND (PGND)
Figure 1. Standard Application Circuit ______________________________________________________________________________________ 13
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
VIN
CONTROL INPUTS VP VMAIN DRVA SEQUENCE CONTROL CT OC OCN OVERCURRENT COMPARATOR VC VLOGIC ONN ONP ON2 ONDC N VSOURCE SHDN IN GATE VC OCP
UVLO AND GATE CONTROL
DRV1 REG 1 WITH SOFT-START AND FAULT COMPARATOR FB1 LX MAIN STEP-UP REGULATOR WITH SOFT-START AND FAULT COMPARATOR CONTROL BLOCK
VMAIN
FB PGND
MAX1997 ONLY VSOURCE DRV2 VGAMMA REG 2 WITH SOFT-START AND FAULT COMPARATOR FB2
VP
DRVP REG P WITH SOFT-START AND FAULT COMPARATOR FBP VVCOM OUTB VCOM BUFFER
VG_ON
VDDB FBPB
FBNB
MAX1997/MAX1998
DRVN REG N WITH SOFT-START AND FAULT COMPARATOR FBN PFLT FREQ GND REF
VG_OFF
REF, OSC, AND BIAS
N.C. N.C.
Figure 2. System Functional Diagram 14 ______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Table 1. Selected Component List
DESIGNATION C2, C13 C4, C5, C6 D1 D2, D3, D4 D5, D6 L1 N1 P1 Q1 Q2, Q3 Q4 DESCRIPTION 10F, 6.3V X5R ceramic capacitors (1206), TDK C3216X5R0J106M 4.7F, 10V X7R ceramic capacitors (1210), Taiyo Yuden LMK352BJ475MF 1.0A, 30V Schottky diode (S-flat), Toshiba CRS02 200mA, 25V dual-series Schottky diodes (SOT23), Fairchild BAT54S 200mA, 75V diode (SOT23), Fairchild MMBD4148 3.0H, 1.3A inductor, Sumida CLS5D11HP-3R0NC 1.9A, 30V N-channel MOSFET (SuperSOTTM-3), Fairchild FDN357P 2.4A, 20V P-channel MOSFET (SuperSOT-3), Fairchild FDN304P 3A, 25V PNP bipolar transistor (SuperSOT-3), Fairchild FSB749 200mA, 40V PNP bipolar transistors (SOT23), Fairchild MMBT3906 200mA, 40V NPN bipolar transistor (SOT23), Fairchild MMBT3904
SuperSOT is a trademark of Fairchild Semiconductor.
Table 2. Component Suppliers
SUPPLIER Fairchild Sumida Taiyo Yuden TDK Toshiba PHONE 408-822-2000 847-545-6700 800-348-2496 847-803-6100 949-455-2000 FAX 408-822-2102 847-545-6720 847-925-0899 847-390-4405 949-859-3963 WEBSITE www.fairchildsemi.com www.sumida.com www.t-yuden.com www.component.tdk.com www.toshiba.com
Standard Application Circuit
The standard application circuit (Figure 1) of the MAX1997 is a complete power-supply system for TFT liquid-crystal displays. The circuit generates 9V for source drivers, +20V and -7V for gate drivers, a 2.5V logic supply for the timing controller, a 8.6V gamma reference voltage, and a VCOM buffer. The input voltage range is from 2.7V to 5.5V. Table 1 lists the selected component options and Table 2 lists the component suppliers.
Detailed Description
The MAX1997 and MAX1998 contain a high-performance step-up switching regulator, two low-cost linearregulator controllers, and multiple levels of protection circuitry. The MAX1997 also includes two additional linear-regulator controllers and a high-current VCOM buffer. Figure 2 shows the MAX1997/MAX1998 system functional diagram. The output voltage of the main step-up regulator (VMAIN) can be set from VIN to 13V with an external resistive voltage-divider. High switching frequency (375kHz/750kHz/1.5MHz) and currentmode control provide fast transient response and allow the use of low-profile inductors and ceramic capacitors.
The low RDS(ON) internal power MOSFET minimizes the external component count and achieves high efficiency using a lossless current-sense architecture. Two charge pumps take energy from the main step-up regulator's switching node (LX) to generate positive and negative supplies. Additional capacitor and diode stages can be used to generate supply voltages greater than +35V and less than -15V. The positive and negative linear-regulator controllers postregulate the charge-pump supply voltages and allow users to program the power-up sequence as well. The high-current VCOM buffer of the MAX1997 is ideal for driving the backplane of a TFT LCD panel. It requires only a 0.47F ceramic output capacitor for stability. The MAX1997's two additional linear-regulator controllers can be used to build the gamma reference and logic supply. The unique input switch control of the MAX1997/ MAX1998 senses the current drawn from the input power supply by monitoring the voltage drop across the input P-channel MOSFET. The protection MOSFET and all regulator outputs latch off if an overcurrent condition lasts for more than the fault timer period.
______________________________________________________________________________________
15
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
FROM OSCILLATOR LX RESET DOMINANT S PGND R Q ILIM COMPARATOR
VLIMIT CURRENT SENSE SLOPE_COMP
FB
TO FAULT LOGIC
1.0V
REFOUT REFIN SOFT-START CLK
REF
Figure 3. Main Step-Up Converter Functional Diagram
In addition, all outputs are monitored for fault conditions that last longer than the fault timer period. The device goes into a latched shutdown state, if the junction temperature of the device exceeds +160C.
The duty cycle of the MOSFET is approximated by: V -V D MAIN IN VMAIN On the rising edge of the internal clock, the controller sets a flip-flop, which turns on the N-channel MOSFET (Figure 3). The input voltage is applied across the inductor. The inductor current ramps up linearly, storing energy in a magnetic field. Once the sum of the feedback voltage, slope-compensation, and current-feedback signals trip the multi-input PWM comparator, the MOSFET turns off, and the flip-flop resets. Since the inductor current is continuous, a transverse potential develops across the inductor that turns on the diode (D1). The voltage across the inductor becomes the difference between the output voltage and the input voltage. This discharge condition forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and the load. The MOSFET remains off for the rest of the clock cycle.
Main Step-Up Controller
The main step-up regulator switches at up to 1.5MHz, and employs a current-mode control architecture to maximize loop bandwidth and provide fast transient response to pulsed loads found in source drivers for TFT LCD panels. In addition, the high switching frequency allows the use of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs. The integrated high-efficiency MOSFET reduces the number of external components. The IC's built-in soft-start function controls the inrush current. Depending on the input-to-output voltage ratio, the regulator controls the output voltage and the power delivered to the output by modulating the duty cycle (D) of the power MOSFET in each switching cycle.
16
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
VMAIN VP VN
DRVP NPN CASCODE TRANSISTOR
PNP PASS TRANSISTOR VG_ON
DRVN
PNP CASCODE TRANSISTOR
NPN PASS TRANSISTOR VG_OFF
FBP
FBN
REF
Figure 4. Using Cascode NPN for Output Voltages > 28V
Figure 5. Using Cascode PNP for Output Voltages < VIN - 28V
Positive Linear-Regulator Controller, REG P
The positive linear-regulator controller is an analog gain block with an open-drain N-channel output. It drives an external PNP pass transistor with a 6.8k base-to-emitter resistor (Figure 1). Its guaranteed base drive sink current is at least 2mA. The regulator is designed to deliver 20mA with an output capacitor of 1F. REG P is enabled when SHDN is high, the gate to the input P-channel MOSFET is low, ONDC is high, VCT > V ONP, and the soft-start of the main step-up regulator is complete. (See the Power-Up Sequencing and Inrush Current Control section.) Each time it is enabled, the regulator goes through a soft-start routine that ramps up its reference input. Note that the voltage rating of the DRVP output is 28V. If higher voltages are present, an external cascode NPN transistor should be used with the emitter connected to DRVP, the base to VMAIN, and the collector to the base of the PNP (Figure 4). REG P is typically used to provide the TFT LCD gate driver's gate-on voltage. A sufficient voltage can be produced using a charge-pump circuit as shown in Figure 1. Use as many stages as necessary to obtain the required output voltage. (See the Selecting the Number of Charge-Pump Stages section.)
REG N is enabled when SHDN is high, the gate to the input P-channel MOSFET is low, ONDC is high, and VCT > V ONN (see the Power-Up Sequencing and Inrush Current Control section). Each time it is enabled, the regulator goes through a soft-start routine that ramps down its reference input. Note that the voltage rating of the DRVN output is VIN - 28V. If lower voltages are present, an external cascode PNP transistor should be used with the emitter connected to DRVN, the base to GND, and the collector to the base of the NPN (Figure 5). REG N is typically used to provide the TFT LCD gate driver's gate-off voltage. A negative voltage can be produced using a charge-pump circuit as shown in Figure 1. Use as many stages as necessary to obtain the required output voltage. (See the Selecting the Number of Charge-Pump Stages section.)
Linear-Regulator Controller, REG 1 (MAX1997 Only)
The linear-regulator controller REG 1 is an analog gain block with an open-drain N-channel output. It drives an external PNP pass transistor with a 510 base-to-emitter resistor (Figure 1). Its guaranteed base-drive sink current is at least 5mA. The regulator is designed to deliver 300mA with an output capacitor of 10F. REG 1 is enabled when SHDN is high and the gate to the input P-channel MOSFET is low. (See the Power-Up Sequencing and Inrush Current Control section.) Each time it is enabled, the regulator goes through a softstart routine that ramps up its reference input. REG 1 is typically used to provide the TFT LCD timing controller's logic supply.
Negative Linear-Regulator Controller, REG N
The negative linear-regulator controller is an analog gain block with an open-drain P-channel output. It drives an external NPN pass transistor with a 6.8k base-to-emitter resistor (Figure 1). Its guaranteed base drive source current is at least 2mA. The regulator is designed to deliver 20mA with an output capacitor of 0.47F.
______________________________________________________________________________________
17
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
VIN IN INPUT CAP VREF 2 GATE
EXTERNAL PFET INDUCTOR INPUT CAP
10A GATE ENABLE
Figure 6. External P-Channel MOSFET Input Switch Control
Linear-Regulator Controller REG 2 (MAX1997 Only)
The linear-regulator controller REG 2 is an analog gain block with an open-drain N-channel output. It drives an external PNP pass transistor with a 2.2k base-to-emitter resistor (Figure 1). Its guaranteed base drive sink current is at least 5mA. The regulator is designed to deliver 30mA with an output capacitor of 2.2F. REG 2 is enabled when SHDN is high, the gate to the input P-channel MOSFET is low, ONDC is high, and V CT > V ON2 . (See the Power-Up Sequencing and Inrush Current Control section.) Each time it is enabled, the regulator goes through a soft-start routine that ramps up its reference input. REG 2 is typically used to provide the TFT LCD gamma reference voltage.
Undervoltage Lockout (UVLO)
To ensure that the input voltage is high enough for reliable operation, the MAX1997/MAX1998 include an undervoltage lockout (UVLO) circuit. The UVLO threshold at the IN pin is 2.7V (typ) rising and 2.35V (typ) falling. The 350mV (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage exceeds the UVLO rising threshold, the controller enables the reference block. Once the reference is above 1.05V, an internal 10A current source pulls the GATE pin low and turns on an external P-channel MOSFET switch (P1, Figure 1) that connects the input supply to the regulator. When the input voltage falls below the UVLO falling threshold, the controller turns off the reference and all the regulator outputs, and pulls GATE high with an internal 100 switch to turn off P1 (Figure 6).
VCOM Buffer (MAX1997 Only)
The MAX1997 includes a VCOM buffer, which is an operational transconductance amplifier that provides a current output for driving the backplane of a TFT LCD panel. The unity-gain bandwidth of this current-output buffer is: GBW = gm/COUT where gm is the amplifier's transconductance, which is the ratio of the output current to the input voltage. The VCOM buffer requires only a 0.47F ceramic output capacitor for stability. The bandwidth is inversely proportional to the output capacitance. Thus, large capacitive loads reduce the bandwidth of the buffer output. In order to improve the transient response time, the amplifier has nonlinear transconductance. The amplifier senses the output current and increases the transconductance as the output current increases. The effect is to provide additional output current when the load demands it.
18
Reference Voltage (REF)
The reference output is nominally 1.25V, and can source up to 75A. (See the Typical Operating Characteristics.) Bypass REF with a 0.22F ceramic capacitor connected between REF and GND.
Oscillator Frequency Control (FREQ)
The internal oscillator frequency is adjustable using the three-level FREQ input. Connect FREQ to ground for 375kHz operation, connect FREQ to VIN for 1.5MHz operation, and leave FREQ unconnected for 750kHz operation. When FREQ is left unconnected, bypass FREQ to ground with a 1000pF to 0.1F capacitor to prevent switching noise from coupling into the pin's high input impedance. Note that the soft-start period scales with the oscillator frequency. (See the Soft-Start section.) The fault timer period does not scale with the oscillator frequency.
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
Shutdown (SHDN)
A logic-low signal on the SHDN pin disables all device functions including the reference. During shutdown, the supply current drops to 0.1A (typ) to maximize battery life. The output capacitance, feedback resistors, and load current determine the rate at which each output voltage decays. A logic-high signal on the SHDN pin activates the MAX1997/MAX1998. (See the Power-Up Sequencing section.) Do not leave the SHDN pin floating. Toggling SHDN (below 0.4V) or cycling IN (below 2.2V) clears the fault latch. (N1, Figure 1), which connects the main step-up regulator output to the source driver's supply pins.
MAX1997/MAX1998
Soft-Start
Each positive regulator (MAIN, REG P, REG 1, and REG 2) includes a 5-bit soft-start DAC whose input is the reference, and whose output is stepped in 32 steps from zero up to the reference voltage. The soft-start DAC of the negative regulator (REG N) steps from the reference down to 125mV in 32 steps. The soft-start duration scales with the switching frequency selected and is 2.73ms for 1.5MHz operation, 5.46ms for 750kHz operation, and 10.92ms for 375kHz operation.
Power-Up Sequencing and Inrush Current Control
Once SHDN is pulled high and the input voltage on IN exceeds the rising input UVLO threshold (2.7V typ), the reference turns on. With a 0.22F REF bypass capacitor, the reference reaches its regulation voltage of 1.25V in approximately 1ms. When the reference voltage is ready, the MAX1997/MAX1998 enable the oscillator and fault detector. After the oscillator is enabled, the controller turns on the external P-channel MOSFET P1 (Figure 1) by pulling GATE low. The GATE is pulled down with a 10A current source. Add a capacitor from the gate of P1 to its drain to slow down the turn-on rate of the MOSFET, which reduces inrush current. To guarantee slow turn-on at lower VIN, add a series resistor between the GATE pin and the gate of the external P-channel MOSFET. The typical value of the resistor ranges between 100k and 200k. Once GATE reaches approximately 0.6V, an internal N-channel MOSFET turns on and pulls GATE to ground in order to maximize the enhancement of the external P-channel MOSFET. After P1 fully turns on, REG 1 and the fault counter are enabled. A logic-high signal on ONDC enables the main step-up regulator and the sequence control block. The sequence control state diagram is shown in Figure 7. The unique sequence control block allows the positive gate-driver voltage (VG_ON), negative gate-driver voltage (VG_OFF), and the source-driver supply voltage (VSOURCE) to be turned on in any order. The capacitor at the CT pin is kept discharged until the main step-up regulator is enabled. An internal 5A current source starts charging the CT capacitor and the CT voltage ramps linearly up to approximately VIN. REG P, REG N, and REG 2 are enabled when the CT voltage exceeds their associated ON_ control inputs. In addition, the positive linear regulator waits for the completion of the main step-up regulator soft-start. The positive linear regulator is controlled by ONP. The negative linear regulator is controlled by ONN. REG2 and the open-drain output DRVA are controlled by ON2. The DRVA signal can be used to turn on an external N-channel MOSFET
SHUTDOWN
SHDN = 0 OR VIN NOT PRESENT
SHDN = 1 AND VIN PRESENT
ENABLE REF, BIAS, AND UVLO
VIN < 2.7V
VIN < 2.7V
VIN > 2.7V
GATE NOT READY
ENABLE OSC, OC COMP, GATE CLEAR FAULT GATE NOT READY GATE READY
ONDC = 0
ENABLE REG 1 AND FAULT COUNTER
ONDC = 0
ONDC = 0 ONDC = 1 BOOST SOFT-START VCT < ON2 DONE AND VCT > ONP ENABLE VCT < ONP BOOST, VCOM, SEQUENCE BLOCK VCT > ON2
ENABLE REG P
VCT > ONN
VCT < ONN
ENABLE REG 2, DRVA HIGH IMPEDANCE
ENABLE REG N
Figure 7. Power-Up Sequence State Diagram 19
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Table 3. Fault Timer Duration
FREQ PIN GND Unconnected IN GND Unconnected IN GND Unconnected IN PFLT PIN* GND GND GND Unconnected Unconnected Unconnected IN** IN** IN** FAULT TIMER DURATION (CLOCK CYCLES) 2
13
FAULT TIMER DURATION (ms) 21.8 21.8 21.8 43.6 43.6 43.6 87.2 87.2 87.2
214 215 214 2
15
216 215 2
16
217
*For MAX1997 only. **The MAX1998 has PFLT internally connected high.
Input Overcurrent Protection
The high-side overcurrent comparator of the MAX1997/MAX1998 provides input overcurrent protection when it is used together with the external P-channel MOSFET switch P1 (Figure 1). Connect resistive voltage-dividers from the source and drain of P1 to GND to set the overcurrent threshold. The center taps of the dividers are connected to the overcurrent comparator inputs (OCN and OCP). See Setting the Input Overcurrent Threshold section for information on calculating the resistor values. An overcurrent event activates the fault-protection circuitry. (See the Fault Protection section.)
device cools down by at least 15C, the fault latch can be cleared to reactivate the device. Toggling SHDN (below 0.4V) or cycling the input voltage (below 2.2V) clears the fault latch.
Design Procedure
Main Step-Up Regulator
Output Voltage Selection Set the output voltage by connecting a resistive voltage-divider from the output (VMAIN) to GND with the center tap connected to FB (see Figure 1). Select R8 to be 1.5k or less for optimized transient response. For higher efficiency, increase R8 to 12k and add lag compensation. (See the Feedback Compensation section.) Calculate R7 with the following equation: R7 = R8 [(VMAIN / VFB) - 1] where VFB = 1.242V - (D x 20mV) and D (VMAIN - VIN) / VMAIN. For example, if VIN = 3V and D 0.66, then V FB = 1.229V. Choosing 1.21k for R8, R7 is 7.65k. Use 7.68k for R7. VMAIN can range from VIN to 13V. Inductor Selection The minimum inductance value, peak current rating, series resistance, and size are factors to consider when selecting the inductor. These factors influence the converter's efficiency, maximum output load capability, transient response time, and output voltage ripple. For a switching frequency of 1.5MHz, use values between 1.8H and 4.7H. For a switching frequency of 750kHz, use values between 3.3H and 8.2H. For a switching frequency of 375kHz, use values between 6.8H and 15H.
Fault Protection
During steady-state operation, if the output of the main regulator or any of the linear-regulator outputs is below its respective fault detection threshold, or an input overcurrent condition occurs, the MAX1997/MAX1998 activate an internal fault timer (Figure 8). If any condition or the combination of conditions indicates a continuous fault for the fault timer duration (see Table 3), the MAX1997/MAX1998 set the fault latch, shutting down all the outputs except the reference and the oscillator. The fault detection circuit is disabled during the softstart time of each regulator. Once the fault condition is removed, toggle SHDN (below 0.4V) or cycle the input voltage (below 2.2V) to clear the fault latch and reactivate the device.
Thermal Shutdown
The thermal shutdown feature limits total power dissipation in the MAX1997/MAX1998. If the junction temperature TJ exceeds +160C, a thermal sensor immediately activates the fault protection (Figure 2) and sets the fault latch, which shuts down all the outputs except the reference, allowing the device to cool down. Once the
20
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
ONDC SHDN UVLO REFERENCE READY THERMAL FAULT R Q S FAULT LATCH GATE READY ENABLES REG 1 LINEAR-REGULATOR GATE
OVERCURRENT FAULT REG 2 FAULT REG 1 FAULT REG P FAULT STEP-UP REGULATOR FAULT REG N FAULT fOSC/128 FREQ PFLT VCT > VONP CLK R RIPPLE COUNTER STEP-UP REGULATOR SOFT-START DONE VCT > VONN VCT > VON2
ENABLES REG 2 LINEAR-REGULATOR
ENABLES STEP-UP REGULATOR
ENABLES REG P LINEAR-REGULATOR
ENABLES REG N LINEAR-REGULATOR
FAULT TIMER
Figure 8. Startup and Fault Protection Logic
The maximum inductor current, input voltage, output voltage, and switching frequency determine the inductor value. To ensure an adequate inductor currentsense signal in the IC, always calculate the inductor value with the maximum guaranteed inductor current even though the actual operating current may be much lower. For the MAX1997/MAX1998, the maximum guaranteed inductor current is the minimum value of the internal LX current limit (1.6A, see the Electrical Characteristics). The equations provided here include a constant defined as LIR, which is the ratio of the peakto-peak inductor current ripple to the average DC inductor current. For a good compromise between the size of the inductor, power loss, and output voltage ripple, select an LIR of 0.3 to 0.5. The inductance value is then given by: VIN(TYP) VMAIN - VIN(TYP) 1 L= VMAIN IL(MAX)fOSC LIR where f OSC is the oscillator frequency (see Electrical Characteristics), and IL(MAX) is 1.6A. Considering the typical application circuit, the typical input voltage is 3.3V, the main output voltage is 9V, and the switching frequency is 1.5MHz. Based on the above equations, the inductance value is 4.3H for an LIR of 0.2. The inductance value is 1.7H for an LIR of 0.5. The inductance in the standard application circuit is chosen to be 3.3H.
The inductor's peak current rating should be higher than the expected peak inductor current throughout the normal operating range. The expected peak inductor current is given by: IMAIN(MAX)VMAIN 1 IPEAK = + VIN(MIN) 1 VIN(MIN) VMAIN - VIN(MIN) 2 VMAIN LfOSC where is the efficiency of the regulator. For most applications, the efficiency is between 75% and 85%. Under fault conditions, the inductor current may reach the internal LX current limit (see Electrical Characteristics). However, soft saturation inductors and the controller's fast current-limit circuitry protect the device from failure during such a fault condition. The inductor's DC resistance can significantly affect efficiency due to the resistive power loss (PLR), which can be approximated by the following equation: I xV PLR = ILAVG2RL MAIN MAIN RL VIN where ILAVG is the average inductor current and RL is the inductor's series resistance. For best performance, select inductors with resistance less than the internal N-channel MOSFET's on-resistance (0.25 typ). To minimize radiated noise in sensitive applications, use a shielded inductor.
21
2
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Output Capacitor The output capacitor affects the circuit's stability and output-voltage ripple. A 15F ceramic capacitor works well in most 1.5MHz applications. Depending on the output capacitor chosen, feedback compensation may be required or desirable to increase the loop phase margin or increase the loop bandwidth for transient response. (See the Feedback Compensation section.) The total output-voltage ripple has three components: the inductive ripple caused by the capacitor's equivalent series inductance (ESL), the ohmic ripple due to the capacitor's equivalent series resistance (ESR), and the capacitive ripple caused by the charging and discharging of the output capacitance. Since the ESL is usually very small, the inductive ripple can be neglected: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) VRIPPLE(ESR) IPEAKRESR(COUT), and V I -V VRIPPLE(C) MAIN MAIN IN COUT VMAINfOSC where I PEAK is the peak inductor current. (See the Inductor Selection section.) For ceramic capacitors, the output voltage ripple is typically dominated by VRIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered. Feedback Compensation Feedback compensation is not needed for the excellent stability and fast transient response of Figure 1's circuit. However, lead or lag compensation can be useful to compensate for layout issues, or optimize the transient response for various output capacitor or inductor values. The loop stability of a current-mode step-up regulator can be analyzed by using a small-signal model. In continuous conduction mode, the loop gain transfer function consists of a DC loop gain, a dominant pole, a right-half-plane (RHP) zero, and an ESR zero. In the case of ceramic output capacitors, the ESR zero is at very high frequency and can be ignored. For stable operation, place the dominant pole at a low enough frequency to ensure that the loop gain reaches unity well before the RHP zero, preferably below one-third of the RHP zero frequency fZ_RHP.
Figure 9. External Compensation
L VIN R9 LX R7 D1 D VMAIN
C9 FB MAX1997 MAX1998 R10 C10 GND PGND C
RL
R8
The frequency of the dominant pole is: 1 fP_DOMINANT = 2RLC where RL is the load resistance and C is the output capacitance; the frequency of the RHP zero is: R fZ_RHP = (1 - D)2 L 2L where D is the duty cycle and L is the inductance; and the DC gain is given by: R8 (1 - D) ADC = 20 x log x x RL R7 + R8 RCS where R CS is the 20m internal equivalent currentsense resistor, and R7 and R8 are the feedback divider resistors in Figure 9. Adding lead compensation (an RC network from VMAIN to FB) increases the loop bandwidth, which can increase the speed of response to transients. Too much speed can destabilize the loop and is not needed or recommended for Figure 1's components. Lead compensation adds a zero-pole pair, providing gain at higher frequencies and increasing loop bandwidth. The frequencies of the zero and pole for lead compensation depend on the feedback divider resistors and the RC network between VMAIN and FB (Figure 9).
22
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
The frequencies of the zero and pole for the lead compensation are: 1 fZ_LEAD = 2 (R7 + R9) x C9 1 fP_LEAD = R7 x R8 2 R9 + x C9 R7 x R8 At high frequencies, R9 is effectively in parallel with R7, determining the amount of added high-frequency gain. If R9 is very large, there is no added gain and as R9 approaches zero, the added gain approaches the inverse of the feedback divider's attenuation. A typical value for R9 is greater than half of R7. The value of C9 determines the frequency placement of the zero and pole. A typical value of C9 is between 100pF and 10nF. When adding lead compensation, always check the loop stability by monitoring the transient response to a pulsed output load. Adding lag compensation (an RC network from FB to ground) decreases the loop bandwidth and improves FB noise immunity. Lag compensation slows the transient response but can increase stability margin, which can be needed for particular component choices, a poor layout, or high values of FB divider resistors (R8 greater than 1.5k). Lag compensation adds a pole-zero pair, attenuating gain at higher frequencies and lowering loop bandwidth. The frequencies of the pole and zero for lag compensation depend on the feedback divider resistors and the RC network between FB and GND (Figure 9). The frequencies of the pole and zero for the lag compensation are: 1 fP_LAG = R7 x R8 2 R10 + x C10 R7 + R8 1 fZ_LAG = 2(R10 x C10) At high frequencies, R10 is effectively in parallel with R8, increasing the divider attenuation ratio. If R10 is very large, the attenuation ratio remains unchanged and as R10 approaches zero, the attenuation ratio approaches infinity. A typical value for R10 is greater than 0.1 times R8. If high-value divider resistors are used, choose R10 < 1.5k for FB noise immunity. The value of C10 determines the frequency placement of the pole and zero. A typical value of C10 is between 100pF and 1000pF. When adding lag compensation, always check the loop stability by monitoring the transient response to a pulsed output load. The circuit of Figure 1 works well without compensation. The circuit of Figure 9 uses lag compensation to allow higher value FB divider resistors, at the expense of transient response speed, potentially requiring higher value output capacitors (see Typical Operating Characteristics). Using one of these two circuits is recommended. Using Compensation for Improved Soft-Start The digital soft-start of the main step-up regulator limits the average input current during startup. If even smoother startup is needed, add a low-frequency lead compensation network (Figure 9). The improved softstart is active only during startup when the output voltage rises. Positive changes in the output are instantaneously coupled to the FB pin through D1 and feed-forward capacitor C9. This arrangement generates a smoothly rising output voltage. When the output voltage reaches regulation, capacitor C9 charges up through R9 and diode D1 turns off. If desired, C9 and R9 can be chosen also to provide some lead compensation in normal operation. In most applications, lead compensation is not needed, and can be disabled by making R9 large. With R9 much greater than R7, the pole and the zero in the compensation network are very close to one another and cancel out after startup, eliminating the effect of the lead compensation. Input Capacitor The input capacitor (CIN) reduces the current peaks drawn from the input supply and reduces noise injection into the device. A 10F ceramic capacitor is used in the standard application circuit (Figure 1) because of the high source impedance seen in typical lab setups. Actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. Typically, CIN may be reduced below the values used in the standard applications circuit. Ensure a low-noise supply at the IN pin by using adequate CIN . Alternatively, greater voltage variation can be tolerated on CIN if IN is decoupled from CIN using an RC lowpass filter (see R1, C1 in Figure 1). Rectifier Diode The MAX1997/MAX1998s' high switching frequency demands a high-speed rectifier. Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. In general, a 1A Schottky diode complements the internal MOSFET well.
MAX1997/MAX1998
______________________________________________________________________________________
23
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
P1 RDS(ON) VIN R2 R4 OCP 100pF OCN OC COMP R3 R5
If the comparator and resistors are ideal, the threshold is at the current where both inputs are equal: R3 R5 VIN x = VIN - IL(MAX) x RDS(MAX) x R2 + R 3 R4 + R5
(
)
IL(MAX) is the average inductor current at maximum load condition and minimum input voltage, and is given by: IL(MAX) = VOUT x ILOAD(MAX) x VIN(MIN)
where is the efficiency of the main step-up regulator. If the step-up regulator's minimum input voltage is 2.7V, the output voltage is 9V, and the maximum load current is 0.3A. Assuming 80% efficiency, the maximum average inductor current is: 9V IL(MAX) = x 0.3A = 1.25A 0.8 x 2.7V R DS(MAX) is the maximum on-state drain-to-source resistance of P1. The maximum RDS(ON) at +25C can be found in the MOSFET manufacturer's data sheet, but that number does not include the MOSFET's temperature coefficient. Since the resistance temperature coefficient is 0.5%/C, RDS(MAX) can be calculated with the following equation: RDS(MAX) = RDS_25C [1 + 0.005 (TJ - 25)] where TJ is the actual MOSFET junction temperature in normal operation due to ambient temperature and selfheating caused by power dissipation. As an example, consider the Fairchild FDN304P, which has a maximum RDS(ON) at room temperature of 70m. If the junction temperature is +100C, the maximum on-state resistance over temperature is: RDS(MAX) = 70m [1 + 0.005 (100 - 25)] = 100m For given R2 and R3 values, the ideal ratio of R4/R5 can be determined: R4 R2 + R 3 VIN - IPEAK(MAX) x RDS(MAX) = x -1 R5 R3 VIN
Figure 10. Setting the Overcurrent Threshold
Input P-Channel MOSFET Select the input P-channel MOSFET based on current rating, voltage rating, gate threshold, and on-resistance. The MOSFET must be able to handle the peak input current (see the Inductor Selection section). The drain-to-source voltage rating of the input MOSFET should be higher than the maximum input voltage. Because the MOSFET conducts the full input current, its on-resistance should be low enough for good efficiency. Use a logic-level or low-threshold MOSFET to ensure that the switch is fully enhanced at the lowest input voltage. Setting the Input Overcurrent Threshold The high-side comparator of the MAX1997/MAX1998 provides input overcurrent protection when used in conjunction with an external P-channel MOSFET P1. The accuracy of the overcurrent threshold is affected by many factors, including comparator offset, resistor tolerance, input voltage range, and variations in MOSFET R DS(ON) . The input overcurrent comparator is only intended to protect against catastrophic failures. This function is similar to an input fuse. To minimize the impact of the comparator's input offset on the current-sense accuracy, the sense voltage should be close to the upper limit of the comparator's common-mode range (same as the operating range), which extends up to 80% of the input voltage. The resistive voltage divider R4/R5, combined with the onstate resistance of P1, sets the overcurrent threshold. The center of R4/R5 is connected to the inverting input (OCN) as shown in Figure 10.
24
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
After including the effects of resistor tolerance, comparator offset, and input voltage variation, the minimum input overcurrent threshold equation is: R 3 x (1 + ) + R2 x (1 + ) + R 3 x (1 + ) 5mV = (VIN(MIN) - IL(MAX) x RDS(MAX) ) x VIN(MIN) x R5 x (1 + ) R4 x (1 + ) + R5 x (1 + ) where VIN(MIN) is the minimum expected value of the input voltage, is the tolerance of the resistors, and 5mV is the worst-case input offset voltage of the comparator. To simplify the equation, define a constant (k) as follows: 1+ k= 1+ The minimum threshold equation becomes: R3 + 5mV = (VIN(MIN) k x R2 + R 3 k x R5 IL(MAX) x RDS(MAX) ) x R4 + k x R5 VIN(MIN) x Solving for R4/R5 yields: VIN(MIN) - IL(MAX) x RDS(MAX) R4 =kx - 1 R5 R3 VIN(MIN) + 5mV R 3 + k x R2 The R4/R5 ratio guarantees the required minimum level for IL(MAX). The typical overcurrent threshold is given by: I TH_TYP = VIN(TYP) RDS(TYP) R3 x (R4 +R5) x 1 R5 x (R2+R3) If R5 =150k, then R4 = 39.2k. The typical overcurrent threshold is:
ITH_TYP = 150 x (39.2k +150) 3.3V x 1 = 4.15A 0.047 150 x (51.1k +150)
MAX1997/MAX1998
Charge Pumps
Selecting the Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meet the output requirement. The number of positive charge-pump stages is given by: NPOS = VG_ON + VDROPOUT - VMAIN VMAIN - 2 x VD
where NPOS is the number of positive charge-pump stages, VG_ON is the positive linear-regulator (REG P) output, VMAIN is the main step-up regulator output, VD is the forward voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 2V. The number of negative charge-pump stages is given by: NNEG = -VG_OFF + VDROPOUT VMAIN - 2 x VD
The following example shows how to apply the above equations in the design. If 1% resistors are used, then = 0.01. To set VOCP to be around 75% of VIN, select R2 = 51.1k and R3 = 150k. Assume that the minimum input voltage is 2.7V and the typical input voltage is 3.3V, the average inductor current at maximum load is 1.25A, and the maximum RDS(ON) of P1 is 100m: 1 - 0.01 k= = 0.9802 1 + 0.01
R4 2.7V - 1.25A x 0.1 = 0.9802 x - 1 150 R5 2.7V x + 0.005V 150 + 0.9802 x 51.1k = 0.2637
where NNEG is the number of negative charge-pump stages, VG_OFF is the negative linear-regulator (REG N) output, VMAIN is the main step-up regulator output, VD is the forward-voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 2V. The above equations are derived based on the assumption that the first stage of the positive charge pump is connected to VMAIN and the first stage of the negative charge pump is connected to ground. Sometimes fractional stages are more desirable for better efficiency. This can be done by connecting the first stage to VIN or another available supply. If the first charge-pump stage is powered from V IN , then the above equations become: NPOS = VG_ON + VDROPOUT - VIN
VMAIN - 2 x VD -VG_OFF + VDROPOUT + VIN NNEG = VMAIN - 2 x VD
______________________________________________________________________________________
25
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Flying Capacitors Increasing the flying capacitor (CX) value increases the output current capability. Increasing the capacitance indefinitely has a negligible effect on output current capability because the internal switch resistance and the diode impedance limit the source impedance. A 0.1F ceramic capacitor works well in most low-current applications. The flying capacitor's voltage rating must exceed the following: VCX > N VMAIN where N is the stage number in which the flying capacitor appears, and VMAIN is the main output voltage. For example, the two-stage positive charge pump in the typical application circuit (Figure 1) where VMAIN = 9V contains two flying capacitors. The flying capacitor in the first stage (C25) requires a voltage rating greater than 9V. The flying capacitor in the second stage (C24) requires a voltage rating greater than 18V. Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. With ceramic capacitors, the output voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value: ILOAD COUT 2fOSCVRIPPLE where VRIPPLE is the peak-to-peak value of the output ripple. Charge-Pump Rectifier Diodes Use Schottky diodes with a current rating equal to or greater than two times the average charge-pump input current. If the loaded charge-pump output voltage is greater than required, some or all of the Schottky diodes can be replaced with low-cost silicon switching diodes with an equivalent current rating. The chargepump input current is: ICP_IN = ICP_OUT N where N is the number of charge-pump stages. Calculate R19 with the following equation: R19 = R20 [(VG_ON / VFBP) - 1] where VFBP = 1.25V. The output voltages of linear regulators REG 1 and REG 2 can be similarly adjusted. Adjust the negative linear-regulator (REG N) output voltage by connecting a resistive voltage-divider from VG_OFF to REF with the center tap connected to FBN (Figure 1). Select R17 in the range of 10k to 30k. Calculate R16 with the following equation: R16 = R17 [(VFBN - VG_OFF) / (VREF - VFBN)] where VFBN = 125mV, VREF = 1.25V. REF can source up to 75A, using a resistor greater than 17k for R17 leaves at least 10A for other uses. Pass Transistor Selection The pass transistor must meet specifications for current gain (), input capacitance, collector-emitter saturation voltage, and power dissipation. The transistor's current gain limits the guaranteed maximum output current to: V I LOAD(MAX) = IDRV - BE MIN RBE where IDRV is the minimum guaranteed base drive current, VBE is the base-to-emitter voltage of the transistor, and RBE is the pullup resistor connected between the transistor's base and emitter. Furthermore, the transistor's current gain increases the linear regulator's DC loop gain (see the Stability Requirements section), so excessive gain destabilizes the output. Therefore, transistors with current gain over 100 at the maximum output current can be difficult to stabilize and are not recommended. The transistor's input capacitance and input resistance also create a second pole, which could be low enough to make the output unstable when heavily loaded. The transistor's saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator supports. Alternatively, the package's power dissipation could limit the usable maximum input-to-output voltage differential. The maximum power dissipation capability of the transistor's package and mounting must exceed the actual power dissipation in the device. The power dissipation equals the maximum load current times the maximum input-to-output voltage differential: P = ILOAD(MAX) (VLDOIN - VLDOOUT) = ILOAD(MAX) VCE
Linear-Regulator Controllers
Output Voltage Selection Adjust the positive linear-regulator (REG P) output voltage by connecting a resistive voltage-divider from VG_ON to GND with the center tap connected to FBP (Figure 1). Select R20 in the range of 10k to 30k.
26
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
Stability Requirements The MAX1997/MAX1998 linear-regulator controllers use an internal transconductance amplifier to drive an external pass transistor. The transconductance amplifier, the pass transistor, the base-emitter resistor, and the output capacitor determine the loop stability. The transconductance amplifier regulates the output voltage by controlling the pass transistor's base current. The total DC loop gain is approximately: 4 I h A V(LDO) = 1 + BIAS FE VREF VT ILOAD where VT is 26mV at room temperature, hFE is the pass transistor's DC current gain, and IBIAS is the current through the base-to-emitter resistor (RBE). Each of the four linear-regulator controllers is designed for a different maximum output current so they have different output drive currents and different bias currents (IBIAS). Each controller's bias current can be found in the Electrical Characteristics. The current listed in the Conditions column for the FB_ Regulation Voltage specification is the individual controller's bias current. The base-to-emitter resistor for each controller should be chosen to set the correct IBIAS: RBE = VBE IBIAS 3) Next, calculate the pole set by the transistor's input capacitance, the transistor's input resistance, and the base-to-emitter pullup resistor: f POLE(CIN) = 1 2CIN(RBE
MAX1997/MAX1998
II RIN )
Because RBE is much greater than RIN, the above equation can be simplified: f POLE(CIN) CIN = gm 2f T 1 2CINRIN
h RIN = R = FE gm where gm is the transconductance of the pass transistor, and fT is the transition frequency. Both parameters can be found in the transistor's data sheet. Therefore, the equation can be further simplified: f POLE(CIN) = fT hFE
The output capacitor and the load resistance create the dominant pole in the system. However, the internal amplifier delay, the pass transistor's input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capacitor's ESR generates a zero. For proper operation, use the following steps to ensure the linear regulator stability: 1) First, calculate the dominant pole set by the linear regulator's output capacitor and the load resistor: f POLE(LDO) = 1 2CLDORLOAD
4) Next, calculate the pole set by the linear regulator's feedback resistance and the capacitance between FB_ and GND (approximately 5pF including stray capacitance): 1 fPOLE(FB)_ P = 2CFB (R19 || R20) 1 fPOLE(FB)_1 = 2CFB (R88 || R99) 1 fPOLE(FB)_ 2 = 2CFB (R11|| R12) and fPOLE(FB)_ N = 1 2CFB (R16 || R17)
where CLDO is the output capacitance of the LDO and RLOAD is the load resistance corresponding to the maximum load current. The unity gain crossover of the linear regulator is: fCROSSOVER = AV(LDO)fPOLE(LDO) 2) The pole caused by the internal amplifier delay is at about 1MHz: fPOLE(AMP) 1MHz
5) Next, calculate the zero caused by the output capacitor's ESR: fESR _ ZERO = 1 2CLDORESR
where RESR is the equivalent series resistance of CLDO.
27
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
VCOM BUFFER VGAMMA RB TO TFT LCD BACKPLANE CB
0.47F
6) To ensure stability, choose CLDO large enough so that the crossover occurs well before the poles and zero calculated in steps 2 to 5. The poles in steps 3 and 4 generally occur at several megahertz and using ceramic capacitors ensures the ESR zero occurs at several megahertz as well. Placing the crossover below 500kHz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual component choices or extra capacitances move the other poles or zero below 1MHz. A capacitor connected between the regulator output and the feedback node can improve the transient response and reduce the noise coupled into the feedback loop (Figure 1). If a low-dropout solution is needed, an external P-channel MOS pass transistor can be used for REG 1. However, a PMOS-based linear regulator requires higher output capacitance to stabilize the loop. The high gate capacitance of the P-channel MOSFET lowers fPOLE(CIN) and can cause instability. A large output capacitor must be used to reduce the unity-gain bandwidth and ensure that the pole is well above the unity-gain crossover frequency. A ceramic capacitor of at least 30F is recommended for VIN = 2.7V, VOUT = 2.5V, and ILOAD = 250mA.
Figure 11. Optimizing VCOM Buffer Drive Current
L VIN
D VOUT
CIN
COUT
GROUND IMPEDANCE
VCOM Buffer
Connect the inverting input FBNB directly to the output OUTB to configure the buffer as a voltage follower. Adjust the buffer's output voltage by connecting a voltage-divider from the gamma reference V GAMMA to GND with the center tap connected to the noninverting input FBPB (Figure 1). Select R14 in the 10k to 100k range. Calculate R13 with the following equation: V R13 = R14 GAMMA - 1 VFBPB The VCOM buffer is designed to be stable with a 0.47F capacitor from OUTB to GND. The charge and discharge currents of the VCOM buffer output can be optimized by adding resistor RB in series with the LCD backplane load and a ceramic capacitor CB (1F or larger) in parallel with the backplane load (Figure 11). Start with a 10 resistor, then gradually increase the value of RB, balancing between display quality and buffer power dissipation. Increasing the value of CB improves the efficiency of the VCOM buffer.
Figure 12. High-Current Loops of Step-Up Regulator
VN
VP
VIN
VMAIN 15V
LX FB STEP-UP REGULATOR PGND
MAX1997 MAX1998
Figure 13. Operation with Output Voltage >13V Using Cascoded MOSFET
28
______________________________________________________________________________________
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
VP
VN
VIN 3.3V TO 5V IN GATE OCN OCP OCN PGND REF REF GND MAX1997 MAX1998 SWITCH CONTROL STEP-UP REGULATOR LX FB
VMAIN +9V
the width of the power ground traces improves efficiency and reduces output voltage ripple and noise spikes. All the other ground connections, such as the IN pin bypass capacitor and the linear-regulator output capacitors, should be star-connected to the backside of the device with wide traces. Make no other connections between these separate ground planes. 3) Place the IN pin and REF pin bypass capacitors as close to the device as possible. 4) Place all feedback voltage-divider resistors as close to their respective feedback pins as possible. The divider's center trace should be kept short. Placing the resistors far away causes their FB traces to become antennas that can pick up switching noise. Care should be taken to avoid running any feedback trace parallel to its associated drive trace or near LX or the switching nodes in the charge pumps. 5) Minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. 6) Minimize the size of the LX node while keeping it wide and short. Keep the LX node away from feedback nodes (FB, FBP, and FBN) and analog ground. Use DC traces as a shield, if necessary. Large ground planes on a multilayer board can provide additional shielding. Refer to the MAX1997 evaluation kit for an example of proper board layout.
MAX1997/MAX1998
Figure 14. Disabling Input MOSFET Switch
Applications Information
PC Board Layout and Grounding
Careful PC board layout is extremely important for proper operation. Use the following guidelines for good PC board layout: 1) The high-current loops of the main step-up regulators are shown in Figure 12. Minimize the area of these loops by placing the input bypass capacitors, output diode, and output capacitors less than 0.2in (5mm) from the LX and PGND pins. Connect these components with traces as wide as possible. Avoid using vias in the high-current paths. If vias are unavoidable, use many vias in parallel to reduce resistance and inductance. 2) Create islands for the analog ground (GND), power ground (PGND), and linear-regulator ground. Connect all three ground areas (islands) at only one location, which is the backside pad of the device. The REF bypass capacitor and all feedback dividers should be connected to the analog ground island (GND). The step-up regulator's input and output capacitors, and the charge-pump components should be a wide power ground plane. The power ground plane should be connected to the power ground pin (PGND) with a wide trace. Maximizing
Additional Application Circuits
Operation with Main Output Voltage >13V The maximum output voltage of the step-up regulator is 13V, which is limited by the absolute maximum rating of the internal power MOSFET. To achieve higher output voltage, an external N-channel MOSFET can be cascoded with the internal FET (Figure 13). Since the gate of the external FET is biased from the input supply, use a logic-level FET to ensure that the FET is fully enhanced at the minimum input voltage. The current rating of the FET needs to be higher than the internal current limit. Disabling Input MOSFET Switch If the input protection MOSFET is not needed, disable the input overcurrent comparator by connecting the OCP pin to ground, and the OCN pin to REF. Leave the GATE pin floating (Figure 14).
______________________________________________________________________________________
29
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer MAX1997/MAX1998
Pin Configurations (continued)
ONDC
Chip Information
TRANSISTOR COUNT: 4704
SHDN
FREQ
GATE
PFLT
OCP
IN
32
31
30
29
28
27
26
25 24 23 22 21
OCN
TOP VIEW
TGNDB PGND DRV1 FB1 CT ONN ONP ON2
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16
TGNDA LX DRVP FBP FB DRV2 FB2 FBPB
MAX1997
20 19 18 17
9
FBNB
OUTB
GND
DRVN
THIN QFN 5mm x 5mm
30
______________________________________________________________________________________
DRVA
VDDB
FBN
REF
Quintuple/Triple-Output TFT LCD Power Supplies with Fault Protection and VCOM Buffer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN 5x5x0.8 .EPS
MAX1997/MAX1998
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
1 2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX1997ETJ

	To Download MAX1997ETJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .